Logic Family built around 1j24b
Logic Family built around 1j24b
Fellow Radiophiles:
The notion of building logic gates with filamentary tubes has intrigued me for a long time. Nearly all Tube based digital computers from the 1950's were built with indirectly heated cathode tubes. Emilio Ciardiello has uncovered evidence of the existence of digital computers with filamentary tubes for low power applications in Avionics. He also found that Raytheon attempted to market some of it's subminiature filamentary tubes for computer use.
The Russian rod tube construction yields very low screen current, typically under 10% of the plate current. This good current gain>10, from screen to plate, made me think of the possibility of building a logic family with tubes that are completely direct coupled from the plate outputs to the screen grid inputs of the next gate. The only additional component is the plate pull-up load resistor. Topologically, this recalls NMOS logic, where the singled ended drain load drives the gate of the next logic element. Perhaps a shaddow grid scheme could have been done with conventionally gridded tubes to achieve a high current gain from G2 to P.
In it's simplest form, a logic family can be built from a single inverting gate with two or more inputs. But, very often, more complex elements like flipflops are customized, as in the use of transmission gates in CMOS flipflops. My approach here is to build a single inverting gate with two or more inputs with a robust Fan-in and Fan-out characteristic.
The gate is in the simple wired NOR configuration. It is easily expanded for more inputs by parallelling more tubes.
The relatively high supply voltage of +90V was paired with the relatively high plate load resistance of 100k, so that 1mA can be pulled by either tube with a screen grid drive of only 50V. The combination of high supply voltage and high load resistance achieve high gain.
The high level voltage without a load is the full supply voltage. When a screen load is present, the logic high is 62V, 55V, 50V when loaded with 1, 2, 3 screen loads respectively. These levels represent the de-facto high logic level. The low logic level is set by the plate saturation between 3V and 5V.
The input resistance of each screen grid exhibits a limiting characteristic that results from the plate saturation at low voltages, but is also >100k when driven with less than a logic high and the plate is not saturated.
The following three curve tracings of the 1j24b show the essential characteristics that are useful to choose bias levels and load resistance for the NOR gate.
The first plot shows plate current as a function of plate voltage and is stepped every 20V at the screen grid G2 up to +100V for the top curve. This gives the essential transconductance from G2 to P around 60uS.
The 100k Load line to the 100V supply intersects a low saturated voltage around +5V when G2 is about 45V.
This plot shows screen grid G2 current as a function of it's voltage, but stepped in 10V steps of plate voltage, up to 50V at the plate. Above 50V at the plate there is negligible effect on screen current. Note how the screen current goes up greatly when the plate drops below the 10V step. Below +10V at the plate, the current is reflected back to the screen grid G2.
Scale: G2=50uA/div, 10V/div
For example, the optimal bias level for G1 is 0V. Increasing G1 to the high side of the filament voltage at 1.3V, increases plate current perhaps 30%, but dramatically increases screen grid G2 current about 4 fold, due to the defocusing effect that the elevated G1 voltage has on the beam. It is clearly not worth boosting plate current 30%, while loosing most of the screen grid G2 current gain. Thus, the control grid G1 bias remains at 0V.
The optimal bias level for G3 was found empirically to be +5V because it boosts screen grid current gain to a maximum, while lowering plate saturation voltage to about 4V. The following curve traces illustrate this in detail.
Scale for 2nd and 3rd plots: G2=50uA/div, 10V/div
The first plot shows the increased plate saturation to +10V at the far left of the plot, when the suppressor grid G3 is biased at 0V, as opposed to +5V when the suppressor grid G3 is biased at +5V shown above.
The second plot shows a doubling of screen current when the suppressor grid is biased at 0V, as opposed to +5V shown above.
The third plot shows the worst possible bias combination, which is with G3=0V and G1=1.3V. This greatly increases screen currents and wipes out most of the screen current gain.
Wolfgang Holtman created the illustration on the left to show beam flow in a typical rod tube.
Note how the rod elements for the two opposing beams are wired together to be driven externally as single elements.
It is very plausible that a directly coupled NOR gate could have been made with a single tube simply by bringing out separate connections for the upper G2 pair and the lower G2 pair. This would produce a direct-coupled NOR gate in a single envelope, but at half the current drive level that would be obtained with two tubes in parallel.
The following set of DC voltage measurements establishes Fan-in and Fan-out for the NOR gates.
A 100k load drives up to 4 NOR inputs (A1, B1, B2, A3). A and B are inputs and QL are outputs. The number indicates which gate.
A1 B1 B2 Q1L=A2 Q2L B+=S=90V G3=5V 100K LOADS VF=1.30V
0 0 0 65.2 3.4
62.5 0 0 3.7 89.2 >unloaded
55.0 55.0 0 2.9 89.2 >unloaded
50.0 50.0 50.0 3.0 3.86
Add A3 load to input A3 Q3L
43.1 43.1 43.1 3.4 8.02 43.1 9.82
Add A4 load to Q2L Q2L=A4 Q4L
43.1 43.1 43.1 3.4 7.98 43.1 9.82 88.6
While driving 4 NOR inputs with a single 100k pull-up, produces valid logic levels. The 9.8V logic lows are almost comming out of saturation. Boosting the supply voltage from 90V to 110V would increase the available pull down current to guaranty that the 100k pull-up could drive four NOR gates to full saturation. This demonstrates a robust Fanout of 4 for 100k pull up to 110V supply.
Further Fanout derating to accomodate filament emission decay over time may also be desirable. However, the screen grid G2 current gain is set largely by rod geometry and bias voltages, not by emission. A weakening tube would exhibit higher voltages for the high and low logic levels.
Fanout can also be boosted by using higher supply voltages and higher load resistors. This would leave the logic high level at the same value as set by the clamping action of G2, but would increase ouput gain for an even more reliably saturated low level.
The following schematic shows a 5 stage ring oscillator to ascertain gate delays. The breadboard construction added 3pF of measured capacitance at each input and output. The oscillation frequency was just under 90kHz, which gives a 2.2us gate delay in the 11uS oscillation period. The 3pF breadboard capacitance account for about 300ns of the 2.2us gate delay.
The following illustrates a simple RS latch made with two NOR gates.
Going Further
While I chose the 1j24b because of it's legendary efficiency, other rod type tubes, like the 1j17b or 1j37b could have been used. The higher current levels of these tubes would have substantially increased speed, about 4 fold. The 1j37b, with it's two control grids, could also be used in a more conventional tube-gate configuration where the inputs are resistively level shifted from the plate to the control grids, and it's screen grid is biased at a fixed level. While this is no longer direct-coupled logic, a single 1j37b embodies a full NAND gate from it's two control grids to the plate.
More can be found at the Russian Subminiature Tubes thread.
Hopefully, this will inspire our more digitally minded fellow Radiophiles to create some interesting all-tube logic design. The tubes are certainly very inexpensive, going for about $1 each on ebay in small lots of 10.
Best regards,
-Joe
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Taking the Logic to the end
If we implement a very basic cpu with 5,000 x 1j24b valves (hypothetically) then compared with EF80 or similar the power is reasonable.
Filament is about 70W
HT about 550W
For EF80 filament of 5,000 parts is about 9000W (assuming you run it slightly low)
Keep up the good ideas Joe. I have appreciated all the other articles you have done on the sub-miniature Russian rod pentodes. It inspired me to make some radio sets. Next I hope to do VHF/MW/LW/SW portable.
Perhaps some of the logic gate ideas could be applied to Stereo Multiplex Decoder though maybe RDS is safer as thought experiment than with 1j24b. However I was planning just a Mono FM/AM set. Discussion of that probably in another thread.
Sadly I'm old enough to remember discrete DTL logic boards. I used to buy them in the market for the parts (possibly 2N706 and IN60 diodes). Each small board was maybe two gates. You would easily fit the same functionality of 1j24b in about the same space. Also though "fatter" (the 8mm tube), illustrations of the military sets show rectangle cut out for the tube, thus saving slightly more than 2mm depth assuming 1.6mm PCB and more than 0.4m of soldered wire on track side.
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